1. Field of the Invention
The present invention relates to information writing for a nonvolatile semiconductor memory, and more particularly to a nonvolatile memory system with improved single-sector erasing.
2. Description of the Related Art
A flash memory, which is a kind of EEPROM (Electrically Erasable Programmable Read Only Memory), employs nonvolatile memory elements, such as MOSFETS, (metal-oxide semiconductor field-effect transistors), each having a control gate and a floating gate. The flash memory stores information in individual memory cells, each constituted by a MOSFET according to the transistor threshold voltage. In such a flash memory, the threshold voltage is set low (logic xe2x80x9c0xe2x80x9d) during the writing operation by putting the drain voltage of the nonvolatile memory element at, for example, 5 V, and by putting the word line connected to the control gate CG at, for example, xe2x88x9210 V as shown in FIG. 18, so as to draw electrical charge from the floating gate FG into the drain region. During an erasing operation, the threshold is set high (logic xe2x80x9c1xe2x80x9d) by putting the well region at xe2x88x925 V, for example, and the control gate CG at a voltage as high as 10 V (logic xe2x80x9c1xe2x80x9d) so as to inject negative charge into the floating gate FG as shown in FIG. 19. Thus, one-bit data is stored in one memory cell.
In a typical conventional flash memory, control gates of a plurality of memory cells are connected to one word line. With the plurality of memory cells connected to the word line as a basic unit (hereinafter called a xe2x80x98sectorxe2x80x99), erasing, writing, and reading operations are performed in respective operating modes. For example, the erasing operation is simultaneously performed in a plurality of memory cells having a common word line, on a sector basis, and a specific memory cell is not selectively erasable.
On the other hand, the conventional writing operation is performed by raising the threshold as shown in FIG. 20(a) after the sector erasing operation has been performed once, applying xe2x88x9210 V to the word line connected to the memory cell whose threshold is to be lowered, and applying 5 V to the drain. As a result, the threshold of the written memory cell becomes lower than the verify voltage Vpv as shown in FIG. 20(b).
Although 0 V is applied to the drains of memory cells that are not written, that is, those whose thresholds are not intended to be lowered, a voltage as great as xe2x88x9210 V is applied to the gates of the other memory cells sharing the word line with the written cell. Consequently, there occurs a phenomenon, called a xe2x80x9cdisturbancexe2x80x9d, in which the threshold is slightly lowered for all of the memory cells connected to the word line. Even memory cells that are not to be written are subjected to a slight threshold voltage change (in this instance, voltage drop), though only the threshold of a specific memory cell to be written is desired to be varied. This disturbance is called a xe2x80x9cdisturbance related to a word linexe2x80x9d, or xe2x80x9cword disturbancexe2x80x9d, since it occurs when voltage is applied mainly to the word line.
Due to the word disturbance, the writing operation requires prior single-sector erasing, as shown with reference to FIGS. 20(a)-20(f). When the plurality of memory cells connected to a common word line are subjected to single-sector erasing initially, the thresholds of the plurality of memory cells are all put in the erased state (FIG. 20(a)). Then, the writing operation is performed so as to put the threshold of a specific memory cell selectively in the written state (FIG. 20(b)). At this time, the plurality of memory cells substantially consist of a first memory cell group whose threshold voltage is in the erased state (shown by a dotted line of FIG. 20(c)) and a second memory cell group whose threshold voltage is in the written state (shown by a dotted line of FIG. 20(d)).
Since the memory cells cannot be erased selectively, only the first memory cell group remains writable. Therefore, any one of the cells in the first memory cell group can be selected and written. Then, when the word disturbance occurs, the threshold voltage of the not-written memory cells is lowered, as shown by a solid line in FIGS. 20(c)-20(d).
If no single-sector erasing is performed, the multiple repetition of disturbance resulting from repeated writing operations lowers the threshold of the memory cell below a word line reading voltage level Vr at the time of reading data, as shown in FIG. 20(e), and causes error data to be read out. Further, the threshold of the memory cell becomes lower than the ground potential Vss, whereby the memory cell is turned ON even though not selected, as shown in FIG. 20(f). When a memory cell connected to a different word line but to a common source line is selected, the charge on the data line flows into the source through the memory cell whose threshold is lower than the aforementioned ground potential Vss, with the result again that error data may be read out.
A system of increasing the threshold of a memory cell through the writing operation is also known, by making the low threshold state an erased state depending on the memory array configuration. However, a disturbance phenomenon still exists in such a writing system because the threshold of a non-written memory cell having a common word line at the time of writing becomes slightly higher (see FIGS. 21(c), 21(d)). When disturbance is repeated several times, the threshold of the memory cell becomes higher than the word line reading level Vr at the time of reading data as shown in FIG. 21(e). Again, error data may be read out.
FIGS. 22(a)-22(f) show an information map of sectors controlled by one word line. As shown in FIGS. 22(a)-22(c), a 512-byte (4096-bit) memory cell is connected to one word line. The effective utilization of the memory can be planned by providing within the same sector a mixture of a storage area (hereinafter called the xe2x80x9csystem areaxe2x80x9d), which is usually not written by general users, for storing OS (operating system) information, sector control information and the like, and a storage area (hereinafter called the xe2x80x9cuser areaxe2x80x9d) to which users are allowed to write information freely. The number of bits in the system area is far smaller than the number of bits in the user area.
In the flash memory of such a storage system, predetermined data is written to the system area, whereas the unwritten user area is offered to the user. It would be convenient to be able to selectively write to the memory cells in the large user area so as to permit repeated xe2x80x9cadditionalxe2x80x9d writing operations, without affecting the already-written system area, and without first erasing the system area. In other words, it would be convenient for the user to be able to write to the unwritten user area without requiring an intermediate sector erase. However, such additional writing operations have not been possible because of disturbance, which prevents the reliability of information stored in the conventional flash memory from being assured.
Even though such additional writing has been conceivable, there has been a substantial limit on the number of additional writing operations to be repeated continuously in consideration of the threshold variation due to the disturbance. By way of example, as few as two consecutive writing operations have compromised the integrity of stored data in the prior art, due to disturbance.
Furthermore, the memory itself has not been designed for use in the manner mentioned above. For this reason, if additional writing is carried out in the conventional flash memory, the time required for the additional writing is extremely long, a burden too heavy for the system software because of the necessity to synthesize the read data and the additional write data, and to write the data combination after reading out the data in the sector involved and then subjecting the sector to single-sector erasing as discussed above.
An object of the present invention is to provide a nonvolatile semiconductor memory that is capable of recovering a variation in the threshold of a memory cell due to disturbance related to a word line.
Another object of the present invention is to provide a nonvolatile semiconductor memory that is capable of continuously performing an additional writing operation without carrying out a single-sector erase for each write.
Still another object of the present invention is to provide a nonvolatile semiconductor memory that is capable of performing an additional writing operation at a speed higher than that which is required for the usual writing operation, lightening the burden imposed on software for use in additional writing.
A brief description will be given of the substance of the invention disclosed in the present specification.
The data stored in a sector at a designated address is read out before being saved in a register, and the sector involved is subjected to single-sector erasing when a predetermined instruction (command) is given. Actual write data (hereinafter called the xe2x80x9cwrite expected value dataxe2x80x9d) is formed from the saved data and data to be additionally written, so that a writing operation is performed.
The flash memory system comprises a plurality of memory cells for storing information in conformity with first and second threshold voltage states. The memory cells are arranged in a functional memory array having a word line connected to control gates of the plurality of memory cells, and a sequencer which has a command input terminal for controlling erase and write operations on information stored or to be stored in the plurality of memory cells in accordance with an instruction which is input to the command input terminal. The instruction that the sequencer receives may be an erase command for collectively putting the plurality of memory cells in the first (erased) state, or an xe2x80x9cadditional write commandxe2x80x9d for selectively changing at least one of the memory cells from the first state to the second state, the additional write command being used for executing not the erase command, but a write operation performed continuously (i.e., a plurality of times without an intervening sector erase).
In a more preferable embodiment of the invention, some of the plurality of memory cells whose threshold voltage is in the first state constitute a first memory group, and the rest constitute a second memory group. According to the additional write command, then, the following steps are taken: The threshold voltage of the memory cells in the second memory cell group is placed between the first state and the second state, and subsequently at least one memory cell selected from those in the first memory cell group is put in the second state, along with those in the second memory cell group.
According to a further preferable embodiment of the invention, the instruction that the sequencer receives includes an erase command for causing a first voltage to be applied to the word line to collectively put the threshold voltage of the plurality of memory cells in the first state. Then, a first write command causes a second voltage to be applied to the word line to put the threshold voltage of memory cells in the selected first memory cell group in the second state, and a second write command causes the first voltage to be applied so as to change the threshold voltage of the plurality of memory cells from the second state to the first state. The second voltage is then applied to the word line to put the threshold voltage of memory cells in the selected second memory cell group in the second state.
Thus, the variation in the threshold voltage of the memory cells due to the word disturbance at the time of the additional writing is recovered, and error data is prevented from being read. Consequently, it is possible to increase greatly the number of times that additional writing is continuously carried out without executing an erasing instruction. By way of example, the present invention is capable of performing 15 consecutive write operations without an intervening sector erase.
By using additional write data fed from the outside and the data read from the selected sector and held in the internal register, the write expected value data is arranged to be automatically formed inside, and then the writing operation is performed. With this arrangement, the additional writing operation can be performed at a speed higher than the ordinary writing, and the burden imposed on software at the time of additional writing is lightened.
These and other objects, advantages, and novel features of the present invention will become apparent from the following detailed description when read in connection with the accompanying drawings.